• Dr. M. DEEPA Ph.d
• Y.BINDU SRAVANI
• K.SIRISHA
• B.HARI NIDHI
• K.Vincent

Clock gating is a well known method to reduce the power in synchronous design. Various arithmetic operations use floating point calculation and can be used for implementation of various computational and logical unit operations. In this proposed work a fused multiply- addition unit is used, which utilizes the common addition block for both addition and multiplication operations. The floating point number is first converted into the IEEE 754 format and then the calculation for both addition and multiplication is performed. The significant is extracted from the number and the calculations are performed on the basis of the exponent difference between the numbers. In the proposed approach a parallel architecture is designed which first extracts the significant and exponent value in the first unit and multiplication-addition operations on the second block. The final output is carried out on the third block where normalization and zero detector operations are performed. In this paper modified square root modified carry select adder is implemented with optimized parameters.

Floating point, clock gating, modified square root carry select adder, zero detector

"ENERGY EFFICIENT DENSITY OPTIMIZED FUSED MAC UNIT USING CLOCK GATING AND MODIFIED SQUARE ROOT CARRY SELECT ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 4, page no.407-411, April-2020, Available :http://www.jetir.org/papers/JETIR2004058.pdf

"ENERGY EFFICIENT DENSITY OPTIMIZED FUSED MAC UNIT USING CLOCK GATING AND MODIFIED SQUARE ROOT CARRY SELECT ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 4, page no. pp407-411, April-2020, Available at : http://www.jetir.org/papers/JETIR2004058.pdf