• A.Sarath Raja
• S.Durga Devi
• K.Mounika
• K.Sai Lokesh

In current technology, VLSI design plays an important role in any Electronic industry, so advanced improvement is needed at every Logic design. In this paper XOR, XNOR based Full-adder design is implemented with 9T level, to overcome the limitations such as power consumption, delay and speed of operation for the Full adders designed using Earlier methods. This 9T based full adder design improves the power, delay and performance parameters. This investigation has been implemented using 25nm technology, full adder design with XOR, XNOR gates. This modern computational design for numerical computations is used to reduce the power and increases the speed of operation which has less delay of 1.67 ms at 5V and power consumption of 4.41mW at 1.5v input and power delay product is 16.8 at 1.5v input.

Full adder XOR and XNOR, 25nm technology,Logic design,Numerical computations,Parameters,Power delay product

"A NOVEL IMPLEMENTATION OF LOW POWER AND FAST FULL ADDER DESIGN USING XOR AND XNOR GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 4, page no.1372-1382, April-2020, Available :http://www.jetir.org/papers/JETIR2004183.pdf

"A NOVEL IMPLEMENTATION OF LOW POWER AND FAST FULL ADDER DESIGN USING XOR AND XNOR GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 4, page no. pp1372-1382, April-2020, Available at : http://www.jetir.org/papers/JETIR2004183.pdf