• BAYYAVARAPU MURALI KRISHNA
• Dr. M. ASHOK KUMAR

This paper proposes a new method for implementing a low power and high speed Carry Skip Adder by means of a set of Gate Diffusion Input (GDI) cell-based multiplexers. Full adder is a very common example of combinational circuits and is used widely in Application Specific Integrated Circuits (ASICs). It is always advantageous to have low power action for the sub components used in VLSI chips. The explored technique of realization achieves a low power high speed design for a widely used subcomponent- full adder. Simulated outcome using state-of-art simulation tool shows finer behavioural performance of the projected method over general CMOS based Carry Skip Adder. Power, speed and area comparison between conventional and proposed Carry Skip Adder is also presented. It is founded that power dissipation is major problem in the electronics device so the goal of this project is to analyse and compare the performance of Carry skip adder using NMOS pass transistor logic configuration and the logic we used in this paper is NMOS pass transistor the configuration in terms of power dissipation, area, and delay. The paper also signifies more than 50% decrement in interconnect length, area, and number of transistor count while using a pass transistor logic in comparison of 4-bit carry skip adder with a CMOS logic configuration.

Low power full adder, 2-Transistor GDI MUX, ASIC (Application Specific Integrated Circuit), 12-TFA, CMOS (Complementary Metal Oxide Semiconductor), Carry Skip Adder, NMOS pass transistor logic, power dissipation, area, delay.

"Design and Implementation of Carry Skip Adder based on low power Techniques ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 7, page no.1101-1107, July 2020, Available :http://www.jetir.org/papers/JETIR2007442.pdf

"Design and Implementation of Carry Skip Adder based on low power Techniques ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 7, page no. pp1101-1107, July 2020, Available at : http://www.jetir.org/papers/JETIR2007442.pdf