• Ritu Singh
• Prashant Chaturvedi

A discrete Hartley transform (DHT) algorithm can be efficiently implemented on a highly modular and parallel architecture having a regular structure is consisting of multiplier and adder. Discrete Hartley Transform (DHT) is one of the transform used for converting data in time domain into frequency domain using only real values. We have proposed a new algorithm for calculating DHT of length 2N, where N=3 and 4. We have implemented Urdhwa multiplier based on compressor as an improvement in place of simple multiplication used in conventional DHT. This paper gives a comparison between conventional DHT algorithm and proposed DHT algorithm in terms of delays and area.

Discrete Hartley Transform (DHT), Urdhwa Multiplier, 4:2 Compressor, 7:2 compressor and Xilinx Vertex family.

"Minimum Path Delay for Discrete Hartley Transform using XOR-XNOR Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 10, page no.562-566, October-2020, Available :http://www.jetir.org/papers/JETIR2010066.pdf

"Minimum Path Delay for Discrete Hartley Transform using XOR-XNOR Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 10, page no. pp562-566, October-2020, Available at : http://www.jetir.org/papers/JETIR2010066.pdf