• P.H.Chandra Mouli
• G.Sankarappa

A novel high-speed and highly reliable sense amplifier- based flip-flop with transition completion detection (SAFF-TCD) is proposed for low supply voltage (VDD) operation. The SAFF-TCD adopts the internally generated detection signal to indicate the completion of sense-amplifier stage transition. The detection signal gates the pull-down path of the sense-amplifier stage and the slave latch, thus overcoming the operational yield degradation, current contention, and glitches of previous SAFFs.The operational yield, speed, hold time, energy consumption, and area of the proposed and previous FFs are quantitatively compared for a wide range of VDD with 22-nm Fin FET technology. It is shown that the minimum VDD of the SAFF-TCD is 573 mV lower than that of previous SAFFs, which means the SAFF-TCD can operate even when VDD is in the near threshold or sub threshold region. At 0.3–0.4 V, the SAFF-TCD operates twice as fast as the master–slave-based FF (MSFF) with a practical hold time.

Flip-flop (FF), low-voltage circuit design, sense amplifier (SA) etc.

"Design of Sense Amplifier using Flip-Flops for Memory Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 10, page no.925-927, October-2020, Available :http://www.jetir.org/papers/JETIR2010121.pdf

"Design of Sense Amplifier using Flip-Flops for Memory Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 10, page no. pp925-927, October-2020, Available at : http://www.jetir.org/papers/JETIR2010121.pdf