• N.Kiran Kumar
• P.H.Chandra Mouli

To achieve higher performance of the CMOS device circuit along with high densities, there have been reductions in supply voltages, device dimensions and transistor threshold voltages over the years. But, these reductions have also resulted in higher leakage currents that can severely affect power consumption in a circuit. Here in this paper we propose an Adiabatic logic circuits with clock gating causes performance enhancement in terms of area, delay or power. Higher switching of clock causes high power consumptions, to reduce the area and power consumption we can have better logic circuits like Adiabatic logics where it results based on stored energy back to the supply. This proposed designs will be implemented in Tanner EDA and the simulated results will be compared with conventional designs.

CMOS Devices, NAND Gate and ECRL Logic, Tanner EDA etc…

"Performance Enhancement in Adiabatic Logics Using 16nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 10, page no.936-940, October-2020, Available :http://www.jetir.org/papers/JETIR2010123.pdf

"Performance Enhancement in Adiabatic Logics Using 16nm CMOS Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 10, page no. pp936-940, October-2020, Available at : http://www.jetir.org/papers/JETIR2010123.pdf