UGC Approved Journal no 63975(19)

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Published in:

Volume 7 Issue 12
December-2020
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2012015


Registration ID:
303997

Page Number

83-88

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Title

Design Of Area Efficient And Low Power 4-Bit Multiplier Based On TG

Abstract

With the rapid advancement in technology, a wide range of high speed mobile computational devices and equipment’s are being introduced in the market. These computational devices strain and drain the battery very quickly. Researchers are making efforts to find ways and means to conserve the battery power for longer period. The core key components in these computational devices are the Adders and Multipliers to support high speed computationally intensive applications in real time. Thus, it becomes more important to reduce power dissipation and area in these Adders and multiplier modules as they affect the performance of the device. This paper presents a design of 4-bit multiplier using full adder cell based on transmission gate adder technique. The proposed adder design consists of a smaller number of transistors compared with full swing gate distribution technique. Therefore, the complete design of the complete adder dissipates the reduced power, while improving the area and ensuring a complete output voltage. The fully proposed adder used to design the Array, Baron and Baugh Wooley multipliers, the power and transistor number of these multipliers has improved compared to the full swing gate diffusion technique.

Key Words

FS XOR-XNOR; FS-GDI; Full Adder; Multiplier; MUX; GDI.

Cite This Article

"Design Of Area Efficient And Low Power 4-Bit Multiplier Based On TG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 12, page no.83-88, December-2020, Available :http://www.jetir.org/papers/JETIR2012015.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design Of Area Efficient And Low Power 4-Bit Multiplier Based On TG", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 12, page no. pp83-88, December-2020, Available at : http://www.jetir.org/papers/JETIR2012015.pdf

Publication Details

Published Paper ID: JETIR2012015
Registration ID: 303997
Published In: Volume 7 | Issue 12 | Year December-2020
DOI (Digital Object Identifier):
Page No: 83-88
Country: -, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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