• N.POOJASREE

In today's digital era, memory is an inevitable part of any integrated device. Also it has a major part in the total circuit power. As the growing concern for portable devices is increasing day by day, the nano-technology is grabbing the eyes of the chip makers. But the drain of power in portable devices which mainly contains static random access memory. As technology scales down Leakage power places important role compared to dynamic power consumption. Hence we used Power gating technique in our Proposed SRAM memory to lower the power consumption which is the need of the day. Also we added another Feature to reduce the leakage power. Since the leakage current of NMOS is larger than that of PMOS with the same feature size. To further reduce the leakage power consumption, instead of using NMOS, the pass transistors of SRAM cells are replaced by PMOSs.

"DESIGN OF 7T SRAM FOR LOW POWER APPLICATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 12, page no.271-276, December-2020, Available :http://www.jetir.org/papers/JETIR2012039.pdf

"DESIGN OF 7T SRAM FOR LOW POWER APPLICATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 12, page no. pp271-276, December-2020, Available at : http://www.jetir.org/papers/JETIR2012039.pdf