• B S Sudha
• Mounika Reddy R

The use of both analog and digital signal is widespread in semiconductor area where most of the researchers are intended to create fast and accurate designs, which include both analog and digital components. Hence, verification of these design is very obvious and it has gained more interest in research domain. Conventional verification methods have a long verification time and a poor level of resilience. This paper presents a UVM verification architecture by using System Verilog for a digital phase-locked loop (DPLL). The characteristics of proposed UVM architecture helps to create a reusable, robust and faster verification environment making faster product release in market. Cadence Incisive Enterprise Simulator was used to create and simulate the testbench. To achieve substantial verification efficiency benefits, the proposed verification architecture employs constrained-random stimulus generation, analog assertions, and coverage metrics. In comparison to standard mixed-signal or analog verification methods, the suggested testbench architecture demonstrated superior verification effectiveness, while concurrently lowering simulation time by an exponential factor. The proposed verification architecture employs limited random real-valued stimulus generation, analogue assertions, coverage metrics, and various test scenarios to achieve significant verification process improvements

Digital signals, Phase Locked Loop (PLL), UVM, Power, Timing, Area

"Verification of digital PLL using UVM Methodology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 11, page no.a184-a190, November-2021, Available :http://www.jetir.org/papers/JETIR2111025.pdf

"Verification of digital PLL using UVM Methodology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 11, page no. ppa184-a190, November-2021, Available at : http://www.jetir.org/papers/JETIR2111025.pdf