• Tirumalareddy Chandra Mouli Swamy
• Koyya suribabu

In this modern era, many digital systems are error-resilient, which allows us to take advantage of approximate computations. It makes the use of replacement of identical computing units by their counterparts. Approximate computing can also decrease the complexity at the designing levels by increasing performance and power efficiency. Adders and multipliers are the basic buildings blocks of many digital applications. These blocks are approximated in several ways. Research works are on the rise at many levels on approximate computing. Approximation at the designing level is more advantageous as the modifications are much easier than the preceding levels. A method of designing an Approximate Multiplier (AM) with a novel structure introduced in a 16-bit adder compressor is proposed. The 16-bit Adder Compressor (AC) is designed with 8-2 adder compressors in general. The 8-2 adder compressor is designed with 7-2 and 3-2 adder compressors and half adders. The existing and proposed multiplier is designed using Xilinx 14.7 in the frontend. The speed of the proposed multiplier is a 55.44% increase compared to Existing Multiplier.

"Efficient Design of Approximate Multiplier using High-Speed Adder Compressor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 11, page no.d169-d174, November-2021, Available :http://www.jetir.org/papers/JETIR2111327.pdf

"Efficient Design of Approximate Multiplier using High-Speed Adder Compressor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 11, page no. ppd169-d174, November-2021, Available at : http://www.jetir.org/papers/JETIR2111327.pdf