• M ANUSHA
• Dr.B.Nageshwar Rao
• Dr.T.Vamsi

When it comes to computing the Discrete Fourier Transform, the Fast Fourier (FFT) is a highly efficient approach (DFT). Field Programmable Gate Arrays (FPGAs) are used to build the fast Fourier transform (FFT) architecture with radix-8 addition and multiplication in TWD of memory-based FFT. The butterflies components BTF0 and BTF1, TWD, and the I/O unit have been studied and optimised. A Spartan3E Gate array FPGA array has been used to implement the FFT in this architecture (FPGA). It was able to pass the simulation and test. In contrast to standard FFT, the proposed design's results are noticeably superior to the latter.

"DESIGN OF EFFICIENT 4096-POINT RADIX 4 MEMORY BASED FFT ARCHITECTURE USING DSP SLICES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.a1-a10, September-2022, Available :http://www.jetir.org/papers/JETIR2209001.pdf

"DESIGN OF EFFICIENT 4096-POINT RADIX 4 MEMORY BASED FFT ARCHITECTURE USING DSP SLICES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppa1-a10, September-2022, Available at : http://www.jetir.org/papers/JETIR2209001.pdf