UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 9 Issue 9
September-2022
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2209002


Registration ID:
501982

Page Number

a11-a19

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Title

HIGH PERFORMANCE BIT-PLANE DECOMPOSITION MATRIX-BASED VLSI INTEGER TRANSFORM ARCHITECTURE FOR HEVC

Abstract

VLSI integer transform structure for High Performance Video Coding (HEVC) processor is proposed in these brief Signed bit-plane transform matrices (SBT) formed from bit-plane decomposition method of integer transform matrices (HEVC) are used to create the architecture. The binary weighted sum of numerous SBT matrices that are simply composed of binary 0 or 1 can be equivalently written as an integer transform matrix. They are relatively simple and have a lesser bit width than that of the original arithmetic transform in form, which is why they are more efficient. There are a lot of zeros in the SBT matrices as well. Using the sparseness of SBT grids is a great way to reduce the number of addition operators. An SBT matrix can be used to transform video data instead of just the original integer transformation in high bit width, as shown here. Thus, the suggested SBT reduces the transform unit circuit's delay greatly. Furthermore, we suggest an adder reuse method for our transform scheme based on the redundancy element character of SBT multipliers, in which the parts are either 0 or -1. Simulated findings suggest that a VLSI transform architecture may be synthesised in a suitable area with a high operating frequency and low latency by utilising the methodologies that have been proposed. The architecture is capable of supporting all real-time HEVC encoders for ultra-high-definition video.

Key Words

Bit-plane matrix, High Efficiency Video Coding (HEVC), integer transform, ultra high definition (HD), very-large-scale integrated (VLSI) architecture

Cite This Article

"HIGH PERFORMANCE BIT-PLANE DECOMPOSITION MATRIX-BASED VLSI INTEGER TRANSFORM ARCHITECTURE FOR HEVC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.a11-a19, September-2022, Available :http://www.jetir.org/papers/JETIR2209002.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"HIGH PERFORMANCE BIT-PLANE DECOMPOSITION MATRIX-BASED VLSI INTEGER TRANSFORM ARCHITECTURE FOR HEVC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppa11-a19, September-2022, Available at : http://www.jetir.org/papers/JETIR2209002.pdf

Publication Details

Published Paper ID: JETIR2209002
Registration ID: 501982
Published In: Volume 9 | Issue 9 | Year September-2022
DOI (Digital Object Identifier):
Page No: a11-a19
Country: Hyderabad, telangana, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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