• Arthi T

A synchronous binary counter is one of the basic components widely used in VLSI design, and it is required to be fast and support a wide bit-width in many applications. However, most of the previous counters are associated with a limited counting rate due to large fan-outs and long carry chains, especially when the counter size is not small. This paper proposes a new fast structure for synchronous binary counting, which has a minimal counting period for practical counter sizes ranging from 8 to 128 bits. We first adopt an 1-bit Johnson counter to reduce the overall hardware complexity, and then duplicate the 1-bit Johnson counter to decrease the propagation delay caused by large fan-outs. Implementation results show that the proposed design can be realized with a small number of flip-flops. This Project describes a more complex timer called the PWM or pulse-width modulation using counter timer. PWM timers are commonly used for motion control and dimming LEDs. Examples of these applications are included here. PWM Function has simplified by Proposed Counter module. This Design is implemented in FPGA XC3S 200 TQ-144 using Verilog HDL and simulated by Modelsim 6.4 c and Synthesized by Xilinx tool.

"Vlsi Implementation of High Speed Pulse Width Modulation using Binary Counter", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.a160-a166, September-2022, Available :http://www.jetir.org/papers/JETIR2209018.pdf

"Vlsi Implementation of High Speed Pulse Width Modulation using Binary Counter", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppa160-a166, September-2022, Available at : http://www.jetir.org/papers/JETIR2209018.pdf