• MEERZA NOUSIN
• Dr.B.Nageshwar Rao
• Dr.T.Vamsi

We offer finite field multipliers with two digits of digits at redundant representations. Performing field multiplication with redundant representation would necessitate extra hardware resources because of the redundancy introduced by embedding in cyclotomic fields. Two new multiplying algorithms and their corresponding designs are suggested to address the problem of repetitive representations in a category of finite fields. In terms of the area-delay product, both of the suggested architectures significantly exceed existing digit-level multipliers based on the same methodology. In addition, it is shown that the suggested multipliers outperform other newly proposed optimum normal basis multipliers in regards of area-delay complexity for a subset of fields. Additional information is provided on the key aspects of the proposed multipliers' postplace&route application-specific integrated circuit implementations for three realistic digit size options

Digit-level architecture, finite field arithmetic, multiplication algorithm, redundant representation

"An Effective Investigation and Optimization of Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.a276-a285, September-2022, Available :http://www.jetir.org/papers/JETIR2209028.pdf

"An Effective Investigation and Optimization of Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppa276-a285, September-2022, Available at : http://www.jetir.org/papers/JETIR2209028.pdf