UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 9 Issue 9
September-2022
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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JETIR2209181


Registration ID:
502403

Page Number

b662-b666

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Title

IMPLEMENTATION OF HIGH-SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS

Abstract

The design of high-performance adders has experienced a renewed interest in the last few years, among high performance schemes, parallel prefix adders constitute an important class. They require a logarithmic number of stages and are typically realized using AND-Orl ogic, moreover with the emergence of new device technologies based on majority logic, new and improved adder designs are possible. However, the best existing majority gate-based prefix adder incurs adelayof2log2(n-1) (due to the nth carry); this is only marginally better than a design using only AND-OR gates (the latter design has a 2log2(n-1) gate delay). This initially shows that delay is caused by the output carry equation in majority gate-based adders that is still largely defined in terms of AND-OR gates. In this, two new majority gate-based recursive techniques are proposed. The first technique is based on a novel formulation of the majority gate-based equations in the employed group generate and group propagate hardware, which results in a new definition for the output carry, resulting in a reduction in latency. The second contribution of this publication reduces the circuit complexity of prefix adder designs by utilising the recursive features of majority gates (via a novel operator). Overall, the proposed methodologies result in the determination of an n-bit adder's output carry with just a log2 majority gate delay (n- 1).

Key Words

IMPLEMENTATION OF HIGH-SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS

Cite This Article

"IMPLEMENTATION OF HIGH-SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.b662-b666, September-2022, Available :http://www.jetir.org/papers/JETIR2209181.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"IMPLEMENTATION OF HIGH-SPEED WALLACE TREE MULTIPLIER USING PARALLEL PREFIX ADDERS ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppb662-b666, September-2022, Available at : http://www.jetir.org/papers/JETIR2209181.pdf

Publication Details

Published Paper ID: JETIR2209181
Registration ID: 502403
Published In: Volume 9 | Issue 9 | Year September-2022
DOI (Digital Object Identifier):
Page No: b662-b666
Country: -, -, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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