• Angad Kumar
• Prof. Ramapati Mishra
• Dr. Shiksha Jain
• Er. Abhishek Srivastava

This project aims to construct a low-power (2.75mw) radio frequency (1.8GHz) Phase Locked Loop (PLL) with a 0.18-µm CMOS era. Current Starved VCO and Differential Pair VCO evaluations have been completed and studied for low and high frequency evaluations, respectively. Spice in the 0.18-µm period created and simulated each aspect of PLL in the Tanner EDA. Both previous designs were simulated in the same environment, and the effects of two maximum critical VLSI restrictions, Speed (High frequency range) and Power intake, were examined. The Differential VCO's fast speed and locking overall performance has been compared to the lower energy consumption benefit of Current starved mainly based VCOs.

Charge pump, Current Starved VCO, PLL, Phase noise and VCO.

"Implementation of 9 Stage Low Power Current Starved Ring VCO", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 10, page no.b578-b582, October-2022, Available :http://www.jetir.org/papers/JETIR2210182.pdf

"Implementation of 9 Stage Low Power Current Starved Ring VCO", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 10, page no. ppb578-b582, October-2022, Available at : http://www.jetir.org/papers/JETIR2210182.pdf