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Published in:

Volume 10 Issue 1
January-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2301181


Registration ID:
507159

Page Number

b604-b610

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Title

Design and Analysis of 15 Transistor SRAM Bit - Cell

Abstract

Power dissipation for nano scale VLSI design is one of the most important perseverance of current. In which continuous transistor scaling with the in growing demand for low powder application for the low voltage coupled circuit. This design expose to environmental condition where vulnerable circuit are the memory, cover the large area silicon dye and storage to critical data. Radiation hardening is one of the most useful for environment condition embedded memory blocks. In various field of application for ultralow powder is of immense important in VLSI chip designing with the reference of 13Transistor SRAM. Radiation hardening of implemented memory block is simply achieved through extremely large cell of bit or redundant array and that maintaining to relatively low power and operating high voltage. In this significant power consumption first four radiation hardened a static random excess memory (SRAM) for high soft error and robust to bit cell low voltage functionality. The proposed is 15Transistor SRAM separated feedback mechanism to apply a novel dwell driven was design and fabricate in 180nm CMOS process. On the basis of the effect single event Latch Up (SEL), Single Event Upset (SEU) and Single Event Transient (SET). Transient current and voltage that arises due to current generating from charge particle are term as SET. In this paper, design simulation of and analysis of radiation harden 15Transistor SRAM is very useful for the market. The total power consumption of 15Transistor SRAM cell is 121.29pw. It is lesser than as compare to my rest paper of 13Transistor SRAM and total power dissipation reduce 33.5% of the total chip of base paper 13Transistor SRAM.

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"Design and Analysis of 15 Transistor SRAM Bit - Cell", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 1, page no.b604-b610, January-2023, Available :http://www.jetir.org/papers/JETIR2301181.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design and Analysis of 15 Transistor SRAM Bit - Cell", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 1, page no. ppb604-b610, January-2023, Available at : http://www.jetir.org/papers/JETIR2301181.pdf

Publication Details

Published Paper ID: JETIR2301181
Registration ID: 507159
Published In: Volume 10 | Issue 1 | Year January-2023
DOI (Digital Object Identifier):
Page No: b604-b610
Country: Bhopal, MP, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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