• Keerthika Nimmakayala

This summary presents an area-efficient tree architecture for finding the first two minima and the indices of the first minima, essential for the design of low-density parity-check decoders based on min-sum algorithms.This proposed architecture decreases the usage of the number of comparators by using the intervening comparison results again and again which are computed for the first minimum to collect second minimum candidates.As a result, the proposed tree architecture significantly improves the spatial-temporal complexity. In this paper, we propose the design of a digital comparator with two different parallel architectures. These comparators are first implemented in Verilog, simulated on the Xilinx ISE 14.6 platform, and then compared to conventional designs. Simulation results shows that the initially proposed architecture decreases the combinatorial delay (logic + interconnect) and the second proposed architecture is even much faster, with a very small combinatorial delay compared to the conventional design. Here in this project, we have extended our project to 128 bit architecture by using 4bit comparator.

Comparator, Multiplexer, Tree based searching module design

"Low Elaboration Tree Architecture for Finding the Initial Minima", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 2, page no.f697-f704, February-2023, Available :http://www.jetir.org/papers/JETIR2302578.pdf

"Low Elaboration Tree Architecture for Finding the Initial Minima", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 2, page no. ppf697-f704, February-2023, Available at : http://www.jetir.org/papers/JETIR2302578.pdf