• K.R.S.Gupta
• P.Gopala Reddy
• K.Usha Maheshwari
• D.Durga sai
• K.Yasasri

The performance and environmental tolerance of CMOS memories are mostly determined by the sense amplifier in combination with memory cells. Sense amplifiers developed become a very big circuits-class due to their significant role in memory design. Two proposed PMOS biased sense amplifier circuits are presented in this paper. Regarding the recital, functionality, and dependability of the memory circuits, sense amplifiers are crucial. The suggested circuit is a PMOS biased sense amplifier that has a very high output impedance, less sense delay, less power dissipation, and performs the same functions as traditional circuits. Tanner EDA was used to simulate and evaluate the proposed sense amplifier's overall performance utilising 45nm library settings.

PMOS Sense Amplifier, Sense delay, Power Consumption.

"LOW POWER PMOS BIASED SENSE AMPLIFIER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 3, page no.h1-h8, March-2023, Available :http://www.jetir.org/papers/JETIR2303701.pdf

"LOW POWER PMOS BIASED SENSE AMPLIFIER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 3, page no. pph1-h8, March-2023, Available at : http://www.jetir.org/papers/JETIR2303701.pdf