UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 10 Issue 8
August-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2308413


Registration ID:
523387

Page Number

e126-e131

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Title

Optimizing Conventional Full Adder Design for Enhanced ALU Performance

Abstract

The adder is a critical component of the ALU and plays a very significant role in determining the performance of a computer system. It is very much required to use an optimized adder for enhanced performance of the ALU and improved overall system performance. This Review paper will show you how various researchers have created a low-power consumption-based adder circuit based on length of transistor. This paper presents a Review on adder circuit design for transistor sizes of 65nm and 90nm. The major goal is to build a prototype for Low Powered VLSI Technology to develop an adder circuit that consumes less power while maintaining high performance than the regular design that uses 28T CMOS logic. The adder is the most basic component of the ALU, and it is used in almost all arithmetic operations. In many cases, it is also used in the implementation of other operations, such as subtraction and multiplication. The performance of the adder directly impacts the performance of the ALU and, therefore, the overall performance of the computer system. A slow or inefficient adder can lead to long wait times for the completion of arithmetic operations, which can result in poor system performance. An optimized adder, on the other hand, can greatly improve the performance of the ALU. By reducing the time, it takes to perform an addition operation, the ALU can complete other operations more quickly, resulting in improved overall system performance.

Key Words

Carry-look ahead adder, ALU, VLSI, CMOS, NMOS, Low-power transistor, Memory Enhancement, Pass Transistor logic, Multiplexer, Power Delay Product

Cite This Article

"Optimizing Conventional Full Adder Design for Enhanced ALU Performance", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.e126-e131, August-2023, Available :http://www.jetir.org/papers/JETIR2308413.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Optimizing Conventional Full Adder Design for Enhanced ALU Performance", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppe126-e131, August-2023, Available at : http://www.jetir.org/papers/JETIR2308413.pdf

Publication Details

Published Paper ID: JETIR2308413
Registration ID: 523387
Published In: Volume 10 | Issue 8 | Year August-2023
DOI (Digital Object Identifier):
Page No: e126-e131
Country: Bengaluru, Karnataka, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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