• Mr. V. Narayana Reddy
• Ch.Anushapriya
• Ch.Pravallika
• B. Venkata Charan
• G.Manikantha

This paper presents the design of an efficient updating mechanism in TCAM for reducing area, time delay and power consumption. It presents two mechanisms for updating FPGA-based TCAM named an accelerated MUX-Update mechanism and a cost-effective LUT-Update mechanism. 64*36 G-AETCAM is designed to enable faster updates with minimized power consumption and area usage. MUX-Update provides an update-latency of W+1 clock cycles by using only three Input/Output (I/O) pins. LUT-Update yields a constant update-latency of 2 clock cycles, independent of the size of TCAM, by using W I/O pins. As an extension of this concept; reversible gate based de- multiplexer design is introduced in-order to reduce power constraints.

"HIGH SPEED G-AETCAM FOR FPGA'S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 4, page no.l110-l112, May-2025, Available :http://www.jetir.org/papers/JETIR2504B16.pdf

"HIGH SPEED G-AETCAM FOR FPGA'S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 4, page no. ppl110-l112, May-2025, Available at : http://www.jetir.org/papers/JETIR2504B16.pdf