UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 5 Issue 9
October-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRA006376


Registration ID:
189277

Page Number

333-336

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Title

DESIGN OF LOW POWER 2:1 MULTIPLEXER WITH MT-CMOS TECHNIQUE

Abstract

Multiplexer with less number of transistors is designed, that will give high speed response and low power consumption. In many applications Multiplexer is used as a universal element, that will collect the data from many sources and transmits to a single destination. In low power techniques, one of the efficient technique is MT-CMOS.In MT-CMOS technique the leakage power is effectively reduced. The operating modes of MT-CMOS are low threshold mode and high threshold mode. The Speed performance is increased by Low threshold mode and the leakage power is reduced by the high threshold mode. By operating sleep bar transistors and sleep transistors with high threshold voltages, the leakage power in MTCMOS circuits can be reduced. When sleep bar input is ON and sleep input is OFF, the current flow in the low threshold voltage main circuit is zero. When sleep bar is OFF and sleep is ON then the circuit works in normal Mode. MT-CMOS technique has low power dissipation 0.011890nwatts compared to traditional 2:1 Multiplexer 1.0308nwatts. Mentor Graphics 130nm technology is used in the design of this circuit.

Key Words

Threshold Voltage, MT-CMOS (Multi Threshold Voltage), Multiplexer, Low Power, 130nm Technology.

Cite This Article

"DESIGN OF LOW POWER 2:1 MULTIPLEXER WITH MT-CMOS TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.333-336, October-2018, Available :http://www.jetir.org/papers/JETIRA006376.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"DESIGN OF LOW POWER 2:1 MULTIPLEXER WITH MT-CMOS TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp333-336, October-2018, Available at : http://www.jetir.org/papers/JETIRA006376.pdf

Publication Details

Published Paper ID: JETIRA006376
Registration ID: 189277
Published In: Volume 5 | Issue 9 | Year October-2018
DOI (Digital Object Identifier):
Page No: 333-336
Country: --, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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