• Dr.R. Solomon Roach
• B Ashok
• G Bhanu Teja,
• Ch Hemanth
• C Sai Maharashi

The FIR digital filters acts as an vital role in the system design of Digital Signal Processing, especially in most of the applications various from medical signal processing to wireless communications. The Finite Impulse Response (FIR) filter is used in the most of the application due the stability and simple in design comparing to Infinite Impulse Response (IIR) filters, the important datapath elements used in the FIR filter is the adders and multipliers.By using pipelining techniques,the latency of the FIR filter is reduced and by parallel processing throughput increases and both the pipelining and parallel processing methods are used for reduce the dynamic power consumption. This project deals with design and implementation of 2-parallel Even Symmetric Parallel Fast FIR (ESPFFIR) filter using Unified Adder subtractor in various high-end FPGAs like Spartan 6, Spartan 6 Low Power, Virtex 6 low power. The multipliers are designed by using Hcub based Multiple Constant Multiplication, BEC- SQRT CSLA and UAS-SQRT CSLA adders are used to reduce the resource utilization and the power consumption of the 2- parallel ESPFFIR filter.The resource utilization, delay and power consumption of the 2-parallel ESPFFIR filter are analyzed using Xilinix ISE 14.7 EDA tool.

MCM, SQRT CSLA, ESPFFIR filter

"FPGA IMPLEMENTATION AND POWER ANALYSIS OF 2-PARALLEL UAS BASED ESPFFIR FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.237-241, April-2019, Available :http://www.jetir.org/papers/JETIRBC06038.pdf

"FPGA IMPLEMENTATION AND POWER ANALYSIS OF 2-PARALLEL UAS BASED ESPFFIR FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp237-241, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06038.pdf