• G.Sujatha
• Dr. Narayanam Balaji

The paper presents a new performance and area optimization algorithm for complex VLSI systems. The Floor planning affords early response that evaluates architectural choices, approximation of chip space, estimates delay, interconnect length and congestion caused by wiring. As technology advances, style complexness is also increasing and hence the circuit size is obtaining larger. Thus, the space of the circuit gets increased and tougher to minimizing the interconnect length. The VLSI necessary design estimates the chip area before the optimized placement of digital blocks and their interconnections. Since VLSI floor planning is an NP-hard problem, several improvement techniques were adopted to find optimal solution. The present research work harnesses a hybrid optimization technique in Ant Colony Optimization (ACO) algorithm is employed for the fixed die outline constrained floor planning, with the ultimate aim of reducing the full chip area. Ant Colony Optimization (ACO) is applied in any stage in genetic algorithm to get an optimum solution for the economical floorplan. The experimental results to achieve global solution for fixed outline constraints took MCNC and GSRC benchmark circuits

Ant Colony Optimization, Non-slicing floor planning, VLSI, MCNC, GSRC

"VLSI CIRCUIT PARTITIONING FOR NON-SLICING FLOOR PLANNING BY USING ANT COLONY OPTIMIZATION TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.325-332, April-2019, Available :http://www.jetir.org/papers/JETIRBC06050.pdf

"VLSI CIRCUIT PARTITIONING FOR NON-SLICING FLOOR PLANNING BY USING ANT COLONY OPTIMIZATION TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp325-332, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06050.pdf