• Arjun R. Savant
• Dr. Milind S. Shah

For the last three decades, the focus of digital design has been primarily on synchronous, clocked architectures. However,as clock rates have significantly increased while feature size has decreased, clock skew has become a major problem.High performance chips must dedicate increasingly larger portions of their area for clock drivers to achieve acceptable skew, causing these chips to dissipate increasingly higher power,especially at the clock edge,when switching is most prevalent.One possible solution to this problem is use of Null Convention Logic(NCL).In this paper,this NCL structure will be compared with the modified NCL structures that are proposed for improvement in parameters like area, speed , delay,energy etc.

-Differential Cascode voltage switch logic NCL, Static holding free NCL, Gate mapping NCL, Low voltage NCL, Static Differential NCL, High speed NCL, Register less NCL, Hybrid Gate diffusion input NCL.

"A Review Paper on Comparison ofConventional Null Convention Logic (NCL) Structure with Modified NCL Structures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 7, page no.172-178, July-2018, Available :http://www.jetir.org/papers/JETIRC006339.pdf

"A Review Paper on Comparison ofConventional Null Convention Logic (NCL) Structure with Modified NCL Structures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 7, page no. pp172-178, July-2018, Available at : http://www.jetir.org/papers/JETIRC006339.pdf