• CH.Sharanya
• M.Praveen kumar
• Dr.D.Lakshmaih
• B. Sanjay Raj
• A.Sharan reddy

In this paper we introduced 10T cmos Full Adder, including the most motivating of those are designed and comparison of area, power and delay. The simulations are approved using 60nm and 90nm technology. Furthermore, design of Borrow Save Adder is introduced to increase the performance better than ripple carry adder. In Microprocessor chip Multiplier is most significant arithmetic design in power dissipation is main parameter. Reducing the power dissipation of multipliers is a key to satisfy the overall power budget of various digital circuits and systems. In this multiplier are CMOS full adder are main building module The main purpose of our work is to calculate the average power, delay and PDP of multiplier. The multiplier architecture will be designed using the 10 transistor Full Adder and the simulation results are compared to existing work our modified proposed multiplier are better performance.

save Adder, Full Adder, Array Multiplier

"Design of Low power CMOS Borrow-Save Adders and 4 bit array multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.40-45, May - 2019, Available :http://www.jetir.org/papers/JETIRCN06008.pdf

"Design of Low power CMOS Borrow-Save Adders and 4 bit array multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp40-45, May - 2019, Available at : http://www.jetir.org/papers/JETIRCN06008.pdf