UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRCO06001


Registration ID:
217157

Page Number

1-5

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Title

Effective and Adaptive Logic Design in VLSI for Digital Circuit Designing using Verilog

Abstract

In digital system design, the main constraint is minimum energy, compatibility, low power, etc. The main objective of the digital design is to achieve Minimum Energy Power system that can obtained by using adaptive logic. In digital circuits the logic used to implement effective designs is adaptive which is a very faster and technological advancement as innovative logic which is been used in almost every digital design to fulfil the major constraints. But additionally Nano sized magneticsystem and CMOS technology is been used to implement the adaptive logic in the digital circuit to extensively improve the efficiency of the energy. In order to achieve the minimum energy techniques the region will be having subsequent threshold and sub-threshold regionsand these both regions will be implemented in adaptive logic. Huge breakpoint of threshold region is in IoT device (Internet of Things) to reduce the power consumption or to increase the yield margins Timing-Error-Detection(TED) systems are been used. If there is conditional minimum voltage, if that is processed in the digital circuit then there will be a scope of occurring delay in the circuit. This delay is further improve as error in the circuit which will be over ridden by using canary circuit which is mainly used for error detection and error correction method, but this canary circuit extents its results in large delay in this regard toovercomethe disadvantage, adaptive logic circuit is been designed with a double gated latchcircuit in each stage of the circuit. This adaptive logic design circuit also undergoes some sought of delay in the circuit which can be over ridden by using a combination of XNOR gate and flip flop in the each section stage to stage for the verification of the signal error. Verilog Coding and implementation process developed by using XILINX ISE 14.3 Version tool.

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"Effective and Adaptive Logic Design in VLSI for Digital Circuit Designing using Verilog ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.1-5, June-2019, Available :http://www.jetir.org/papers/JETIRCO06001.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Effective and Adaptive Logic Design in VLSI for Digital Circuit Designing using Verilog ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp1-5, June-2019, Available at : http://www.jetir.org/papers/JETIRCO06001.pdf

Publication Details

Published Paper ID: JETIRCO06001
Registration ID: 217157
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 1-5
Country: c, d, India .
Area: Engineering
ISSN Number: 2349-5162


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