UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRDF06008


Registration ID:
223810

Page Number

28-31

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Title

Reliable Multiplier Design Implementation On FPGA With Adaptive Hold Logic

Abstract

Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with novel adaptive hold logic (AHL) circuit. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 ×16 column-bypassing multipliers or with 16 × 16 row-bypassing multipliers. In Proposed System an aging-aware reliable multiplier design is inserted with a novel adaptive hold logic (AHL) circuit. The multiplier is based on the variable-latency technique. The AHL circuit is to achieve reliable operation under the influence of NBTI and PBTI effects. This architecture can be applied to fourier transform, discrete cosine transforms and digital filtering. The adaptive hold logic (AHL) can be implemented in FPGA Spartan 3/ Spartan 3AN and is simulated in ModelSim6.4c and Xilinx 9.1/13.2 software using Verilog HDL (VHDL). It has an advantage of minimizing the performance degradation and reducing the delay produced in the multiplier. For future enhancement, a RS-Encoder based design can be introduced in the multiplier.

Key Words

NBTI, PBTI, Adaptive Hold Logic, Verilog HDL, FPGA

Cite This Article

"Reliable Multiplier Design Implementation On FPGA With Adaptive Hold Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.28-31, June 2019, Available :http://www.jetir.org/papers/JETIRDF06008.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Reliable Multiplier Design Implementation On FPGA With Adaptive Hold Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp28-31, June 2019, Available at : http://www.jetir.org/papers/JETIRDF06008.pdf

Publication Details

Published Paper ID: JETIRDF06008
Registration ID: 223810
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 28-31
Country: Chennai, Tamil Nadu, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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