• Monika Mehra
• R P Singh

This article offers a comparative 2:1 multiplexer analysis of logic styles of three distinct technologies, 45nm and 32nm and 16nm (transmission door, transistor and CMOS logic). Synopsys HSPICE tool with 1V power supply is used to simulate. As a consequence, the 2:1 multiplexer used by TGL consumes the least power. The transistor logic consumes 99.7% less power than PTL and 99% more power than CMOS consumes. Since the PTL multiplexer uses minimal number of transistors, 2, the size of the efficient 2:1 MUX logic circuit is therefore low performance as its output is slightly distorted. Two key objectives for the 2:1 MUX design are being achieved in the comparative research. The first is that transistors are lower, and the second aim is that energy consumption is minimum. The investigation is performed with 1V energy supply from Synopsys HSPICE using three separate technologies: 45nm, 32nm and 16nm. As a result, TGL's 2:1 multiplexer is the least power consumption.

2:1 Multiplexer, Circuits, CMOS logic, Design, Power Consumption, Transistors.

"2:1 Multiplexers Using Various Styles of Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 9, page no.239-244, September 2018, Available :http://www.jetir.org/papers/JETIRFH06041.pdf

"2:1 Multiplexers Using Various Styles of Design", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 9, page no. pp239-244, September 2018, Available at : http://www.jetir.org/papers/JETIRFH06041.pdf