ISSN: 2349-5162 | Impact Factor: 5.87

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Published in:

Volume 4 Issue 4
April-2017
eISSN: 2349-5162

Unique Identifier

JETIR1704006

Page Number

21-23

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Title

By Using VHDL Implementation Of Reed Solomon Encoder & Decoder For Wireless Network 802.16

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Abstract

The reed Solomon codes can detect & correct error with in blocks of data. Channel coding for error detection & correction help the communication system designers to reduce the effect of a noisy transmission channel. The aim of this paper implementation of reed solomon error detecting & correcting code by using VHDL language Berlekamp-Massey Algorithm are the main components. This operation based on Field Programmable gate array (FPGA)

Key Words

Reed-Solomon codes; code generator polynomials; syndrome; Berlekamp Massey; Chien; IEEE 802.16; VHDL;FPGA

Cite This Article

"By Using VHDL Implementation Of Reed Solomon Encoder & Decoder For Wireless Network 802.16", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.4, Issue 4, page no. pp21-23, April-2017, Available at : www.jetir.org & http://www.jetir.org/JETIR1704006

Publication Details

Published Paper ID: JETIR1704006
Registration ID: 170167
Published In: Volume 4 | Issue 4 | Year April-2017
DOI (Digital Object Identifier):
Page No: 21-23
ISSN Number: 2349-5162

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UGC and ISSN Approved Journal | Call For Paper
(Volume 4 | Issue 12 | December 2017 |Impact factor 5.87)

Call For Paper | Volume 4 | Issue 12 | Impact factor 5.87


Important Dates Related to Publication Procedure:
  • » Paper Submission Till: 29 December 2017.
  • » UGC and ISSN Approved Journal
  • » Review (Acceptance/Rejection) Notification: Within 02-04 Days.
  • » Paper Publish:Within 02-07 Days after submitting the all documents.
  • » Frequency: Monthly (12 issue Annually)
  • » Journal Type : Open Access
  • » Publication Charges : 1300 INR
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