ISSN: 2349-5162 | Impact Factor: 4.14

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Published in:

Volume 4 Issue 4
April-2017
eISSN: 2349-5162

Unique Identifier

JETIR1704006

Page Number

21-23

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Title

By Using VHDL Implementation Of Reed Solomon Encoder & Decoder For Wireless Network 802.16

Abstract

The reed Solomon codes can detect & correct error with in blocks of data. Channel coding for error detection & correction help the communication system designers to reduce the effect of a noisy transmission channel. The aim of this paper implementation of reed solomon error detecting & correcting code by using VHDL language Berlekamp-Massey Algorithm are the main components. This operation based on Field Programmable gate array (FPGA)

Key Words

Reed-Solomon codes; code generator polynomials; syndrome; Berlekamp Massey; Chien; IEEE 802.16; VHDL;FPGA

Cite This Article

"By Using VHDL Implementation Of Reed Solomon Encoder & Decoder For Wireless Network 802.16", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.4, Issue 4, page no.21-23, April-2017, Available :http://www.jetir.org/papers/JETIR1704006.pdf

Publication Details

Published Paper ID: JETIR1704006
Registration ID: 170167
Published In: Volume 4 | Issue 4 | Year April-2017
DOI (Digital Object Identifier):
ISSN Number: 2349-5162

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