UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 11 | Issue 4 | April 2024

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 5 Issue 10
October-2018
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1810644


Registration ID:
190404

Page Number

248-255

Share This Article


Jetir RMS

Title

OPTIMIZATION OF MAC UNIT USING FULL PIPELINED ACCUMULATOR: A REVIEW

Abstract

With the rapid advancements in real time signal processing and digital signal processing, low power and high throughput circuitry plays a vital and challenging role for the designer. For a high performance digital signal processing system it is essential to have a MAC unit with gigantic speed and enormous throughput. The fundamental motivation of this work is to examine the full pipelined multiplier/ accumulator architecture and circuit design techniques which are suitable for achieving high throughput and with low power consumption. MAC unit comprises of multiplier, adder and accumulator/register. MAC based on the existing techniques has high delay due to accumulator without being affected by the large scale research and models. Henceforth, in this proposed framework we incorporated Carry Save Adder (CSA) technique considering various parametric constraints to assure the feasibility, efficiency and effectiveness in comparison with the existing methods. In a pipelined MAC unit, the delay estimation will assist in identifying the overall delay of the pipelined MAC unit. Many researches on the multiplier architectures including array, parallel and pipelined multipliers validates that pipelining is the most widely used technique to reduce the propagation delays of digital circuits. Therefore, the main motivation of this research is to investigate fully pipelined multiplier/accumulator architecture and circuit design technique which is suitable for implementing high throughput signal processing algorithms and at the same time achieve low power consumption.

Key Words

Multiplier & accumulator (MAC), floating point, booth multiplier, vedic multiplier, array multiplier, verilog HDL.

Cite This Article

"OPTIMIZATION OF MAC UNIT USING FULL PIPELINED ACCUMULATOR: A REVIEW ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.5, Issue 10, page no.248-255, October-2018, Available :http://www.jetir.org/papers/JETIR1810644.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"OPTIMIZATION OF MAC UNIT USING FULL PIPELINED ACCUMULATOR: A REVIEW ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.5, Issue 10, page no. pp248-255, October-2018, Available at : http://www.jetir.org/papers/JETIR1810644.pdf

Publication Details

Published Paper ID: JETIR1810644
Registration ID: 190404
Published In: Volume 5 | Issue 10 | Year October-2018
DOI (Digital Object Identifier):
Page No: 248-255
Country: Nagpur, Maharashtra, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0003012

Print This Page

Current Call For Paper

Jetir RMS