• M.N. Bhavana
• J. Prasad Babu

MAC unit performs both multiply and addition capabilities. This is frequently demanded in Digital Signal Processing applications. The multiply- accumulate (MAC) unit operates in two ranges, Firstly it calculates the manufactured from given numbers and feed the end result to the following stage of operation i.E. Addition or called as accumulation. If both the ranges are carried out in a single spherical then it is called fused multiply- accumulate (fMAC) unit. A lot of researches had been completed and performing on MAC implementation. In this paper we gift a brand new design of approximate multiplier that is utilized in MAC to reduce the hardware complexity of the Design. Moreover, the proposed multipliers are compared with exact multipliers, outperforming in performance parameters like area, delay and power consumption, for similar error values. The simulation results are shown in Cadence EDA tool with 90nm technology libraries.

DTMAC, DSP, ECSM, FPGA, MAC, VLSI.

"A LOW-POWER HIGH-SPEED APPROXIMATE MULTIPLIER FOR MAC APPLICATIONS ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.149-156, May-2019, Available :http://www.jetir.org/papers/JETIR1905R22.pdf

"A LOW-POWER HIGH-SPEED APPROXIMATE MULTIPLIER FOR MAC APPLICATIONS ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp149-156, May-2019, Available at : http://www.jetir.org/papers/JETIR1905R22.pdf