• Dr.M.Deepa
• K.Savikhya

In this work presented an ultra-low power 12 bit asynchronous analog to digital converter with successive approximation technique. The major design consists of five blocks those are non- binary array of capacitors, retiming clock generation unit, comparator, self-timed loop and SAR logic. These all blocks are utilized to decline the power consumption and delivers the accurate results. In this non-linear capacitance correction method and latch output glitch removal correlation method has been employed, SAR logic gives the improved speed of operations and reduces the power consumption by 1.2mW in a 32-nm CMOS technology.

successive approximation register (SAR), capacitor array ADC, 32-nm CMOS technology

"A 12-BIT SAR ADC WITH NON-LINEAR CAPACITANCE DAC SWITCHING SCHEME IN 32-nm CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 3, page no.1127-1132, March-2020, Available :http://www.jetir.org/papers/JETIR2003167.pdf

"A 12-BIT SAR ADC WITH NON-LINEAR CAPACITANCE DAC SWITCHING SCHEME IN 32-nm CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 3, page no. pp1127-1132, March-2020, Available at : http://www.jetir.org/papers/JETIR2003167.pdf