• Fariha Fatma
• Abu rehan

In this digital world rather than construction, testing the built architecture has became the challenging task. Testing process includes high cost and power consumption. Many studies have taken part in construction of efficient testing circuits, in that BIST is one of the efficient testing circuit. BIST [Built in Self Test] provides a platform for testing the circuit with low power consumption and with spending fewer bucks. The construction of the BIST is done with the MULTISTAGE LFSR decoder circuits, which makes a path in testing the circuit by providing random and complete input sequences to the built architecture. The decoding logic is also employed to make it perfect for fault tolerant architecture.The pavement made of the BIST with MULTISTAGE lfsr is said to be the efficient technique in finding the faults in the working of the circuitry so this is termed as the fault tolerant architecture the construction of the proposed architecture is done in Xilinx ISE proceeding with verilog HDL language.

Index Terms—BIST, MULTISTAGE lfsr , decoding logic, linear-feedback shift register (LFSR), Bench mark circuit.

"ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 9, page no.680-687, September-2020, Available :http://www.jetir.org/papers/JETIR2009090.pdf

"ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 9, page no. pp680-687, September-2020, Available at : http://www.jetir.org/papers/JETIR2009090.pdf