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Published in:

Volume 7 Issue 9
September-2020
eISSN: 2349-5162

Unique Identifier

JETIR2009090

Page Number

680-687

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Title

ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY

ISSN

2349-5162

Cite This Article

"ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 9, page no.680-687, September-2020, Available :http://www.jetir.org/papers/JETIR2009090.pdf

Abstract

In this digital world rather than construction, testing the built architecture has became the challenging task. Testing process includes high cost and power consumption. Many studies have taken part in construction of efficient testing circuits, in that BIST is one of the efficient testing circuit. BIST [Built in Self Test] provides a platform for testing the circuit with low power consumption and with spending fewer bucks. The construction of the BIST is done with the MULTISTAGE LFSR decoder circuits, which makes a path in testing the circuit by providing random and complete input sequences to the built architecture. The decoding logic is also employed to make it perfect for fault tolerant architecture.The pavement made of the BIST with MULTISTAGE lfsr is said to be the efficient technique in finding the faults in the working of the circuitry so this is termed as the fault tolerant architecture the construction of the proposed architecture is done in Xilinx ISE proceeding with verilog HDL language.

Key Words

Index Terms—BIST, MULTISTAGE lfsr , decoding logic, linear-feedback shift register (LFSR), Bench mark circuit.

Cite This Article

"ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 9, page no. pp680-687, September-2020, Available at : http://www.jetir.org/papers/JETIR2009090.pdf

Publication Details

Published Paper ID: JETIR2009090
Registration ID: 300770
Published In: Volume 7 | Issue 9 | Year September-2020
DOI (Digital Object Identifier):
Page No: 680-687
ISSN Number: 2349-5162

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Cite This Article

"ARCHITECTURAL DESIGN OF BIST USING MULTISTAGE LFSR ALGORITHM IN VLSI TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 9, page no. pp680-687, September-2020, Available at : http://www.jetir.org/papers/JETIR2009090.pdf




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