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Published in:

Volume 7 Issue 9
September-2020
eISSN: 2349-5162

Unique Identifier

JETIR2009363

Page Number

462-468

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Title

An Assessment on Delay and Power in Sequential Circuits and Efficient Designing Architectures

ISSN

2349-5162

Cite This Article

"An Assessment on Delay and Power in Sequential Circuits and Efficient Designing Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 9, page no.462-468, September-2020, Available :http://www.jetir.org/papers/JETIR2009363.pdf

Abstract

Sequential circuits are the key component in most of the VLSI system. Power utilization is a major task in integrated circuits. Behaviour of the sequential circuits depends upon the clock signals. Hence the clock signal contributes to the delay in the circuit and power dissipation because of the internal transistors. Power minimization techniques need to be used in the circuit design for efficient working. Here we have discussed in detail the types of delay and the sources of power dissipation and the techniques to measure it. We have also mentioned some predefined models that are effective in reducing the delay and power dissipation in the sequential circuit. This paper is the review of the existing techniques that are used to design a low power and high-speed synchronous circuit. The prime focus of our work is to summarizing the circuit performance characteristics like delay, power, and area utilization.

Key Words

Sequential Circuit, Delay, Power Dissipation, Adiabatic Logic, Clock Gating, Power Gating, Dual-Edge Triggering, Near-Threshold Voltage.

Cite This Article

"An Assessment on Delay and Power in Sequential Circuits and Efficient Designing Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 9, page no. pp462-468, September-2020, Available at : http://www.jetir.org/papers/JETIR2009363.pdf

Publication Details

Published Paper ID: JETIR2009363
Registration ID: 301488
Published In: Volume 7 | Issue 9 | Year September-2020
DOI (Digital Object Identifier):
Page No: 462-468
ISSN Number: 2349-5162

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Cite This Article

"An Assessment on Delay and Power in Sequential Circuits and Efficient Designing Architectures", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 9, page no. pp462-468, September-2020, Available at : http://www.jetir.org/papers/JETIR2009363.pdf




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