• Manikanta Umadevi
• T.Reddy Rani
• N.Nagendra

In the field of VLSI, enhancement is prominent. Arithmetic circuits are one of the influential sectors in today’s end products of electronics, where multipliers are one of the deciding factors of efficiency. Multiplier plays an important role in different applications such as digital signal processing in which it acts as a key hardware block. As time rolls down, the technology exposed the ways for the initiation of many hardware and software implementations of the faster multipliers. One among them is the Montgomery multiplier. The fundamental operation in the Montgomery multiplier is the modular multiplication. It is mainly used in FIR filters, which in-turn has numerous applications such as speech analysis, multi-rate signal processing, adaptive filters, and averaging filters. With the usage of proposed compressor in the conventional design of the multiplier, the number of transistor count has been declined by a significant amount and made the design into an optimal area design. This paper presents a modified Montgomery multiplier design and its implementation in the 5 th order FIR filter.

Cryptography, Montgomery Multiplier, Compressor, FIR Filter

"An implementation of FIR filters using Digit-Serial Montgomery multipliers and Asute Compressors for Digital signal processing applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 11, page no.d792-d796, November-2022, Available :http://www.jetir.org/papers/JETIR2211408.pdf

"An implementation of FIR filters using Digit-Serial Montgomery multipliers and Asute Compressors for Digital signal processing applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 11, page no. ppd792-d796, November-2022, Available at : http://www.jetir.org/papers/JETIR2211408.pdf