• K.Jhansi Rani
• B. Hemanthnag

The increasing complexity of digital signal processing (DSP) systems demands higher computational performance. However, traditional DSP arithmetic has limitations in terms of speed. In some applications, speed is more important than accuracy. To further enhance performance, approximate arithmetic circuits are designed with some loss of accuracy to reduce energy consumption and increase speed. These approximate circuits are suitable for error-tolerant applications. In this paper, we propose a modified decoder-based approximate multiplier (MDBAM) that uses a decoder-based encoder at the partial product generation stage. The proposed multiplier simplifies the multiplication operation, which reduces area and increases speed. The proposed and existing designs are coded in Verilog HDL and synthesized and simulated using the Xilinx Vivado 2016.4 environment.

Decoder-Based encoder, adders, Approximate computing.

"Modified Decoder-Based Approximate Multiplier for High-Speed Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 9, page no.f418-f423, September-2023, Available :http://www.jetir.org/papers/JETIR2309550.pdf

"Modified Decoder-Based Approximate Multiplier for High-Speed Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 9, page no. ppf418-f423, September-2023, Available at : http://www.jetir.org/papers/JETIR2309550.pdf