• Harish Babu DS
• Dr. Yogesh G S
• Dr.Anita R

this paper. We recommend a truncationbased approximation multiplier with a compensation circuit made by specific k-map changes to prevent the carry caused by the truncated component. Hardware trimming and output error reduction are completed simultaneously. Using simplified NAND gate circuits, 16x16 truncated multipliers based on sequential approximation multipliers are produced for error correction. We provide a unique segmentation technique for signed SSM. We present a straightforward, hardwareeffective multiplier correction method. This design is implemented using Verilog HDL, and it is simulated using ModelSIM 6.4c. To gauge performance, the Xilinx Tool performs the Synthesis Process.

"LOW POWER DESIGN OF EDGE DETECTOR USING STATIC SEGMENTEDAPPROXIMATE MULTIPLIERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 10, page no.e83-e85, October-2023, Available :http://www.jetir.org/papers/JETIR2310324.pdf

"LOW POWER DESIGN OF EDGE DETECTOR USING STATIC SEGMENTEDAPPROXIMATE MULTIPLIERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 10, page no. ppe83-e85, October-2023, Available at : http://www.jetir.org/papers/JETIR2310324.pdf