• Aishwarya S K
• Meera A

This paper implements a 3-bit resolution Flash Analog to Digital Converter. The developed Flash ADC includes memristor-based encoders and 3-stage magnitude comparator, and the entire design was created using the Lt-Spice tool. The resistive ladder network is exposed to a 1.2V reference voltage. The flash ADC uses a two-stage pre-amplifier as a comparator. The main issue that typically arises in flash ADC is that as the number of resolution bits increases, so does the circuit's size and power consumption. As a result, we primarily focused on optimizing the encoder circuitry to lower the ADC's power consumption. Encoder is implemented utilizing MRL to decrease the area in order to save power consumption. Calculated and compared are the Flash ADC's performance metrics, including delay, average power, and transistor count.

Analog to Digital Converter (ADC), Memristor ratioed logic (Memencoder), Three stage Comparator

"Design of Low Power Flash ADC Using Memristor Based Encoder and Three Stage Comparator", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 10, page no.f452-f458, October-2023, Available :http://www.jetir.org/papers/JETIR2310454.pdf

"Design of Low Power Flash ADC Using Memristor Based Encoder and Three Stage Comparator", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 10, page no. ppf452-f458, October-2023, Available at : http://www.jetir.org/papers/JETIR2310454.pdf