• Twinkle Singh

This paper presents a Comparison of different optimization techniques and sanity checks in logical synthesis. In the Very Large Scale Integration (VLSI) industry, synthesis is a very important step in the design process. It entails translating a high-level design specification into a netlist of gates that can be physically implemented with electronic components like transistors. The heart of the modern electronics industry is the System on Chip (SoC), which is expected to be worth 500 billion dollars by 2028 at an annual growth rate of 8.05 percent. It comprises a few Application-specific integrated circuits (ASICs) on a similar wafer. Different functionalities can be displayed as various modules or blocks on an SoC. In an SoC plan cycle, union structures the connection between the front-end configuration part and the backend plan part as it plays out the most vital phase in changing over the plan code in the actual structure in terms of a netlist. Timing analysis plays a crucial role in determining whether the design requirements' timing parameters are met

System on Chip; ASICs; VLSI;

"COMPARISON OF DIFFERENT OPTIMIZATION TECHNIQUES AND SANITY CHECKS IN LOGICAL SYNTHESIS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 2, page no.e581-e590, February-2024, Available :http://www.jetir.org/papers/JETIR2402481.pdf

"COMPARISON OF DIFFERENT OPTIMIZATION TECHNIQUES AND SANITY CHECKS IN LOGICAL SYNTHESIS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 2, page no. ppe581-e590, February-2024, Available at : http://www.jetir.org/papers/JETIR2402481.pdf