• Anil G. Sawant
• Dr. Vilas N. Nitnaware
• Pranali Dengale
• Sayali Garud
• Akshay Gandewar

In this paper, a novel VLSI architecture of the TWOFISH block cipher is presented. TWOFISH is one of the most secure cryptographic algorithm. The characteristic features of the TWOFISH Algorithm are good security margin and has fast encryption/decryption in software, moderately fast in hardware and moderate flexibility. Based on the loop-folding technique combined with efficient hardware mapping, the architecture of twofish Algorithm can make data encryption/ decryption more efficient and secure. To demonstrate the correctness of our Algorithm , a prototype chip for the architecture has been implemented. The chip can achieve an encryption rate and low power consumption while operating clock rate. Designed TWOFISH cryptographic algorithm improved the MDS block that improved a process speed, and decreased complexity and power consumption. Therefore, the chip can be applied to encryption in high-speed networking protocols like ATM networks. This paper will be implemented in Xilinx 14.2 in Verilog HDL.

Verilog , MDS, PHT, DES, Function F and h.

"TWOFISH ALGORITHM FOR ENCRYPTION AND DECRYPTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.288-291, January-2019, Available :http://www.jetir.org/papers/JETIRW006063.pdf

"TWOFISH ALGORITHM FOR ENCRYPTION AND DECRYPTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp288-291, January-2019, Available at : http://www.jetir.org/papers/JETIRW006063.pdf