• SARAVANA KUMAR M

— Packet scheduling algorithms in switches and routers play a critical role in providing the Quality-of-Service (QoS). The combination of fairness, efficiency and low-latency makes Arbiter an attractive scheduling discipline for both best-effort and guaranteed-rate services. The interconnection network also supports random routine that allows the data connection to be routed automatically around the busy ports. In addition, the interconnection network provides broadcast facility which allows one node to send a message to all destination nodes it can used in general network interface applications. In this paper a Wrapped Wave Front Arbiter using Virtual Cut technique and a crossbar are designed. The result of the arbiter and the crossbar architecture is obtained using Xilinx 14.1 ISE design suite and its area, power and delay are calculated. Comparison between the existing routers has less area and delay with 7% of accuracy. Also Layout is generated using cadence SoC Encounter in 180nm technology.

FIFO, Arbiter, Controller, Crossbar.

"DESIGN AND SIMULATION OF ROUTER USING WRAPPED WAVEFRONT ARBITER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 1, page no.19-24, June-2014, Available :http://www.jetir.org/papers/JETIR1401004.pdf

"DESIGN AND SIMULATION OF ROUTER USING WRAPPED WAVEFRONT ARBITER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 1, page no. pp19-24, June-2014, Available at : http://www.jetir.org/papers/JETIR1401004.pdf