• Trivedi Shivangi
• Parmar Harekrishna
• Shah Sneha

Test Time minimization is crucial problem for a System on Chip (SOC). Test Time Minimization could be obtained by arranging the cores in appropriate manner. The System-on-A-Chip (SOC) revolution challenges both design and test engineers in the area of power dissipation as well as in the area of test time. Test time could be minimized through the test scheduling technique. Test scheduling is crucially important for the optimal SOC. The minimization of test time of SOC is done through Test Scheduling. This work focuses the arrangement of the External cores as well as BIST cores of SOC such that the reduction in test time could be obtained. The arrangement of core takes care of the implicit dead time as well as explicit dead time. Efficient test schedules minimize the overall system test application time and limit power dissipation during test mode. Minimization of test time is becoming increasingly important in today’s systems design and is a major goal in the future development of new designs. This Paper shows how the core should be arranged to have reduction of test time in SOC.

SOC, BIST, External Core, Test time.

"Scheduling of Core for Reduction of Test Time in SOC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 7, page no.867-870, December-2014, Available :http://www.jetir.org/papers/JETIR1407053.pdf

"Scheduling of Core for Reduction of Test Time in SOC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 7, page no. pp867-870, December-2014, Available at : http://www.jetir.org/papers/JETIR1407053.pdf