• Krishna J Parmar
• Prof. Hardik H. Makwana

The growing complexity of Multiprocessor Systems on Chips (MPSoCs) is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. The effectiveness of this approach largely depends on the availability of a design methodology.With technology scaling, as the geometries of the transistors reach the physical limits of operation, another important design challenge of SoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The interconnect will be susceptible to various noise sources such as cross-talk, coupling noise, process variations, etc.. Designing systems under such uncertain conditions becomes a challenge.Therefore, the goal is to solve some of the most important and time intensive problems encountered during NOC design can be solved with Fault tolerant Router.. While preserving the throughput, the network load, and the data packet latency of NOC router.

Fault Tolerant router, VLSI Architecture, and FPGA

"Design and Implementation of Fault Tolerant Router for Network On Chip using FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.2, Issue 5, page no.1654-1661, May-2015, Available :http://www.jetir.org/papers/JETIR1505058.pdf

"Design and Implementation of Fault Tolerant Router for Network On Chip using FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.2, Issue 5, page no. pp1654-1661, May-2015, Available at : http://www.jetir.org/papers/JETIR1505058.pdf