• Nitesh Kumar
• Debasish Halder
• Mohan Kumar

A low power dynamic comparator capable of detecting a minimum input voltage difference of 100μV is presented in this article. The comparator is designed and simulated with a supply voltage of both 0.4 V and 1.2 V using UMC 180 nm CMOS technology. All the transistors are compelled to work in the sub-threshold region while working with the supply voltage of 0.4 V. But in case of 1.2 V supply voltage it works in normal region. It consumes 74.09nW power at a frequency of 2 MHz and 136.2 ns delay with a of 0.4 V supply voltage while in case of 1.2 V it consumes 155.70 µW power at a frequency of 500 MHz and 381ps delay

Double-tail comparator, dynamic clocked comparator, ultra-low power, sub-threshold, biosensors, bioelectronics, implantable devices

"A Novel Approach of Low Power Low Voltage Dynamic Comparator Design for Biomedical Application ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 1, page no.4-9, January-2016, Available :http://www.jetir.org/papers/JETIR1601002.pdf

"A Novel Approach of Low Power Low Voltage Dynamic Comparator Design for Biomedical Application ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 1, page no. pp4-9, January-2016, Available at : http://www.jetir.org/papers/JETIR1601002.pdf