UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 8 | Issue 6 | June 2021

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 3 Issue 10
October-2016
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1610036


Registration ID:
160476

Page Number

227-239

Share This Article


Jetir RMS

Title

AGING-AWARE RELIABLE MULTIPLIER DESIGN WITHADAPTIVE HOLD LOGIC

Abstract

Digital multipliers are among the most critical arithmetic functional units. The overall performance of these systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability effect occurs when a pMOS transistor is undernegative bias (Vgs= −Vdd), increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations. Therefore, it is important to design reliable high-performance multipliers. In this paper, we propose an aging-aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide higher throughput through the variable latency and can adjust the AHL circuit to mitigate performance degradation that is due to the aging effect. Moreover, the proposed architecture can be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed architecture with 16 × 16 and 32 × 32 column-bypassing multipliers can attain up to 62.88% and 76.28% performance improvement, respectively, compared with 16×16 and 32×32 fixed-latency column-bypassing multipliers. Furthermore, our proposed architecture with 16 × 16 and 32 × 32 row-bypassing multipliers can achieve up to 80.17% and 69.40% performance improvement as compared with 16×16 and 32 × 32 fixed-latency row-bypassing multipliers. In addition we removed the tristate buffer from the coloumn by pass multiplier. So that we can reduced the gate count and improve the efficiency and speed and reduce the power consumption.

Key Words

Adaptive hold logic (AHL), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), reliable multiplier, variable latency.

Cite This Article

"AGING-AWARE RELIABLE MULTIPLIER DESIGN WITHADAPTIVE HOLD LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 10, page no.227-239, October-2016, Available :http://www.jetir.org/papers/JETIR1610036.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"AGING-AWARE RELIABLE MULTIPLIER DESIGN WITHADAPTIVE HOLD LOGIC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 10, page no. pp227-239, October-2016, Available at : http://www.jetir.org/papers/JETIR1610036.pdf

Publication Details

Published Paper ID: JETIR1610036
Registration ID: 160476
Published In: Volume 3 | Issue 10 | Year October-2016
DOI (Digital Object Identifier):
Page No: 227-239
Country: --, --, -- .
Area: Engineering
ISSN Number: 2349-5162


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0002494

Print This Page

Current Call For Paper

Jetir RMS