UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 8 | Issue 6 | June 2021

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 3 Issue 10
October-2016
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR1610037


Registration ID:
160477

Page Number

240-247

Share This Article


Jetir RMS

Title

Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT in FPGA Technology

Abstract

Approximation of discrete cosine transform (DCT) is useful for reducing its computational complexity without significant impact on its coding performance. Most of the existing algorithms for approximation of the DCT target only DCT of smaller lengths and some of them are nonorthogonal. This paper presents a generalized recursive algorithm to obtain orthogonal approximation of DCT where an approximate DCT of length could be derived from a pair of DCTs of length at the cost of additions for input preprocessing. We perform recursive sparse matrix decomposition and make use of the symmetries of DCT basis vectors for deriving the proposed approximation algorithm. Proposed algorithm is highly scalable for hardware as well as software implementation of DCT of higher lengths, and it can make use of the existing approximation of8-point DCT to obtain approximate DCT of any power of two length,. We demonstrate that the proposed approximation of DCT provides comparable or better image and video compression performance than the existing approximation methods. It is shown that proposed algorithm involves lower arithmetic complexity compared with the other existing approximation algorithms. We have presented a fully scalable reconfigurable parallel architecture for the computation of approximate DCT based on the proposed algorithm. One uniquely interesting feature of the proposed design is that it could be con figured for the computation of a 32-point DCT or for parallel computation of two 16-pointDCTs or four 8-point DCTs with a marginal control overhead. The proposed architecture is found to offer many advantages in terms of hardware complexity, regularity and modularity. Experimental results obtained from FPGA implementation show the advantage of the proposed method.

Key Words

Algorithm-architecture code sign, DCT approximation, discrete cosine transform (DCT), high efficiency video coding (HEVC)

Cite This Article

"Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT in FPGA Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 10, page no.240-247, October-2016, Available :http://www.jetir.org/papers/JETIR1610037.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT in FPGA Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 10, page no. pp240-247, October-2016, Available at : http://www.jetir.org/papers/JETIR1610037.pdf

Publication Details

Published Paper ID: JETIR1610037
Registration ID: 160477
Published In: Volume 3 | Issue 10 | Year October-2016
DOI (Digital Object Identifier):
Page No: 240-247
Country: --, --, -- .
Area: Engineering
ISSN Number: 2349-5162


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0002479

Print This Page

Current Call For Paper

Jetir RMS