• N.VEDA KUMAR
• THEEGALA DHIVYA

Now a day’s many of technologies handles low power consumption to meet the requirements of various outboard applications. In these applications, a multiplier is a fundamental arithmetic unit and used in a great extent in circuits. Multipliers are key components of many high performance systems such as FIR filters, Microprocessor, digital signal processors etc. Booth algorithm is used for design of multiplier but it suffers from some limitations like number of the partial products increases, so area and time delay also increases. To cut down the number of Calculation steps for the partial products, Modified Booth Algorithm [MBA] have been employed. [1] In this paper various techniques and algorithms are analyzed for design of multiplier in terms of delay, area and power consumption.

Booth multiplier, Reversible logic gate, Multiplier and-Accumulator (MAC), Modified booth algorithm.

"Review of Booth Algorithm for Design of Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.3, Issue 10, page no.248-253, October-2016, Available :http://www.jetir.org/papers/JETIR1610038.pdf

"Review of Booth Algorithm for Design of Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.3, Issue 10, page no. pp248-253, October-2016, Available at : http://www.jetir.org/papers/JETIR1610038.pdf