• SUJATHA H
• PALLAVI B

The main aim of our work is to design and implementation of a physically feasible hardware system to accelerate the processing speed of the operations required for real time face detection. Therefore, it has resulted in the development of a real-time face detection system employing an FPGA implemented system designed by Verilog HDL.In this project we present hardware architecture for real-time face detection system. We propose hardware design techniques to accelerate the processing speed of face detection. The face detection system generates an integral image window to perform a Haar feature classification during one clock cycle. And then it performs classification operations in parallel using Haar classifiers to detect a face in the image sequence.

"REAL TIME FACE DETECTION USING FPGA ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.1, Issue 5, page no.1-8, October-2014, Available :http://www.jetir.org/papers/JETIR1701994.pdf

"REAL TIME FACE DETECTION USING FPGA ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.1, Issue 5, page no. pp1-8, October-2014, Available at : http://www.jetir.org/papers/JETIR1701994.pdf