• Gurpadam Singh
• Dr Neelam Rup Prakash

In this paper a higher order FIR filter is designed with a digital filter design tool in Matlab/Simulink for given specifications. An equivalent model is developed with the help of Xilinx System Generator blocks in the Matlab/Simulink environment. For simulation appropriate parameters are set in the Simulink model. The simulation of the filter is completed with Digital Filter Design tool as well as with Xilinx FIR Compiler. The implementation results are obtained by setting Optimization Goal: first as Speed and then as Area in the Xilinx ISE Design Suite. A comparative evaluation of implementation with Optimization Goal: Speed vs Area is carried out based on Place and Route Report, Post-PAR Static Timing Report and Xilinx XPower Analyzer’s Power Report.

FIR Filter, higher order FIR filter, FPGA.

"FPGA Implementation of Higher Order FIR filter: Speed vs Area ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.4, Issue 8, page no.12-19, August-2017, Available :http://www.jetir.org/papers/JETIR1708004.pdf

"FPGA Implementation of Higher Order FIR filter: Speed vs Area ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.4, Issue 8, page no. pp12-19, August-2017, Available at : http://www.jetir.org/papers/JETIR1708004.pdf